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Changelog

svd2rust

Generate Rust register maps (`struct`s) from SVD files

NewAugust 15, 2025

v0.37.0

Fix new mismatched-lifetime-syntaxes lint warnings
Adapt RISC-V specific codegen for riscv-peripheral v0.3.0 rework
Include riscv-peripheral peripherals in Peripherals struct
repr(transparent) for field wrapper
Ensure __INTERRUPTS are #[no_mangle] on Xtensa.
Add base_isa field to riscv_config to allow the riscv_rt::core_interrupt macro to properly generate start trap assembly routines in vectored mode.
Add edition flag

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