Added

• Script to align all the elf sections to the AXI Data Width (the testbench requires it)
• RISC-V V intrinsics can now be compiled
• Add support for vsetivli, vmv<nr>r.v instructions
• Add support for strided memory operations
• Add support for stores misaligned w.r.t. the AXI Data Width

Changed

• Alignment with lowRISC's coding guidelines
• Update Ara support for RISC-V V extension to V 0.10, with the exception of the instructions that were already missing
• Replace toolchain from GCC to LLVM when compiling for RISC-V V extension
• Update toolchain and SPIKE support to RISC-V V 0.10
• Patches for GCC and SPIKE are no longer required
• Ara benchmarks are now compatible with RISC-V V 0.10

Fixed

• Fix vrf_seq_byte definition in the Load Unit
• Fix check to discriminate a valid byte in the VRF word, in the Load Unit
• Fix axi_addrgen_d.len calculation in the Address Generation Unit
• Correctly check whether the generated address corresponds to the vector load or the store unit
• Typos on the ChangeLog's dates
• Remove unwanted latches in the addrgen, simd_div, instr_queue, and decoder
• Fix vl == 0 memory operations bug. Ara correctly tells Ariane that the memory operation is over