ara

Fixed

• Fix typo on the build instructions of the README
• Fix Gnuplot installation on GitHub's CI
• The number of elements requested by the Store Unit and the Element Requester now depends both on the requested eew and the past eew of the vector of the used register
• When the VRF is written and EMUL > 1, the eew of all the interested registers is updated
• Memory operations can...

Fixed

• Fix calculation of vstu's vector length
• Fix vslideup and vslidedown operand's vector length trimming
• Mute mask requests on idle lanes
• Mute instructions with vector length zero on the respective lane_sequencer and operand_requester
• Fix simd_div's offset calculation
• Delay acknowledgment of memory requests if the axi_inval_filter is busy

Added

• F...

Added

• Script to align all the elf sections to the AXI Data Width (the testbench requires it)
• RISC-V V intrinsics can now be compiled
• Add support for vsetivli, vmv<nr>r.v instructions
• Add support for strided memory operations
• Add support for stores misaligned w.r.t. the AXI Data Width

Changed

• Alignment with lowRISC's coding guidelines
• Update Ara support for R...

Added

• Hardware support for:
  • Vector slide instructions (vslideup, vslide1up, vfslide1up, vslidedown, vslide1down, vfslide1down)
• Software implementation of a integer 2D convolution kernel
• CI job to check the conv2d execution on Ara

Fixed

• Removed dependency to a specific gcc g++ version in Makefile
• Arithmetic and memory vector instructions with vl == 0 are considered...

Added

• Parametrization for FPU and FPU-specific formats support, through the FPUSupport ara_soc parameter