Features

• Expose read-latency and write-latency parameters of FIRRTL memories (by @trmckay in https://github.com/chipsalliance/chisel/pull/5133)

Fixes

• Use DedupGroup Phase in ChiselStage$ (by @seldridge in https://github.com/chipsalliance/chisel/pull/4728)
• Add a workaround to verification directory path problem on Windows and firtool 1.138.0 (by @Siudya in https://github.com/chipsalliance/chisel/pull/5134)
• [svsim] Fix deadlock in long simulations by flushing expectation queue (by @Emin017 in https://github.com/chipsalliance/chisel/pull/5132)

Documentation

• Bump qs from 6.14.0 to 6.14.1 in /website (by @dependabot[bot] in https://github.com/chipsalliance/chisel/pull/5136)

Dependency Updates

• [cd] Bump CIRCT from firtool-1.138.0 to firtool-1.139.0 (by @chiselbot in https://github.com/chipsalliance/chisel/pull/5140)

Build and Internal Changes

• [main] Enable MiMa for v7.6.0 (by @chiselbot in https://github.com/chipsalliance/chisel/pull/5131)

Full Changelog: https://github.com/chipsalliance/chisel/compare/v7.6.0...v7.7.0