chisel

Features

• Add noModulePrefix (by @trmckay in https://github.com/chipsalliance/chisel/pull/5147)
• Add chisel3.SimulationTestHarnessInterface and chisel3.SimulationTestHarness (by @trmckay in https://github.com/chipsalliance/chisel/pull/5155)
• Add FlattenInstanceAllowDedup (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/5162)
• layer: add requireNotElideBlocksContext. (by @dtz...

Features

• Expose read-latency and write-latency parameters of FIRRTL memories (by @trmckay in https://github.com/chipsalliance/chisel/pull/5133)

Fixes

• Use DedupGroup Phase in ChiselStage$ (by @seldridge in https://github.com/chipsalliance/chisel/pull/4728)
• Add a workaround to verification directory path problem on Windows and firtool 1.138.0 (by @Siudya in https://github.com/c...

Features

• [core] Add associate method for Seq of ports (by @seldridge in https://github.com/chipsalliance/chisel/pull/5122)
• Add runpath option to UnitTests main (by @fabianschuiki in https://github.com/chipsalliance/chisel/pull/5125)

Backend Code Generation

• Fix name prefixing from views on rhs of connection (by @jackkoenig in https://github.com/chipsalliance/chisel/pull/5117) Previ...

API Deprecation

• Move ExtModule and Params out of experimental (by @seldridge in https://github.com/chipsalliance/chisel/pull/5099)
• [core] Deprecate ExtModule, Params in experimental (by @seldridge in https://github.com/chipsalliance/chisel/pull/5101)
• [core] Deprecate ExtModule utility traits (by @seldridge in https://github.com/chipsalliance/chisel/pull/5102)
• [core] Deprecate BlackBox...

API Modification

• Make object Type in ClassType public (by @adkian-sifive in https://github.com/chipsalliance/chisel/pull/5075) Update object Type in properties ClassType to be public
• Add SimulationTest marker (by @fabianschuiki in https://github.com/chipsalliance/chisel/pull/4849)

Fixes

• [svsim] Use filelist for source files (by @seldridge in https://github.com/chipsalliance/chisel...