Updated VHDL and created Verilog generator for RAM component with byte-enables
Added VHDL and Verilog for the RAM component with line-enables
fixed clasic appearance shift-register bug
Added automatic custom Logisim library loading at startup.
Created unit tests for loading custom Logisim libraries at startup.
Updated documentation for the automatic loading of custom Logisim libraries.
New take on project export/import. A zip-file is generated which can include a user provided "README.md".
Added Telnet component.
Added Metal graphics acceleration option.
Added option to hide/show toolbar
Improved drawing appearance.
Fixed TTY appearance bug while changing various zoom levels.
Corrected appearance of NOT gates in TikZ/SVG image export.
Corrected disjoint corners in arrow-style Pins.
Improved output of rectangles with rounded corners in TikZ image export.
Fixed Undo/Redo issues.
Fixed Power-on-Reset propagation issue.
Version 4.0.0 - logisim-evolution Release Notes | AnnounceHQ
Redesigned simulation engine to fix synchronization issues and increase speed.
Fixed synchronization and efficiency issues in wires and propagation.
Fixed synchronization and efficiency issues in propagation listeners.
Limited redraws to about 20 frames per second to reduce overhead.
Allows users to choose a simulation queue, which changes the efficiency of the simulator depending on circuit design.
Simplified Type and Behavior attributes of Pins.
This change will break circuits with input pins that need to pull floating values to 0 but do not
have the Pull Down setting. To fix it, set the Behavior attribute to Pull Down.
Updated Pin documentation.
Subcircuits with clock input(s) are now drawn with a clock symbol.