logisim-evolution

• v4.0.0 (2025-09-07)
  • Updated VHDL and created Verilog generator for RAM component with byte-enables
  • Added VHDL and Verilog for the RAM component with line-enables
  • fixed clasic appearance shift-register bug
  • Added automatic custom Logisim library loading at startup.
    • Created unit tests for loading custom Logisim libraries at startup.
    • Updated documentation for the au...

• Updated Java requirement to Java 21.
  • Added an autosave feature along with preferences for it.
  • Added a new preference to allow the user to choose the action keys for many functions.
  • Changed RAM default output from error to undefined [#1747]
  • Added support for scanning 7-segment display on FPGA-boards
  • Added first support for the openFpga toolchain for the ecp5 famely...

Mainly a bug-fix release:

• Added reset value attribute to input pins
• Fixed boolean algebra minimal form bug
• Fixed random fill Rom bug
• Added TTL 74164, 74192 and 74193.
• Fixed off grid components bug that could lead to OutOfMemory error.
• Removed autolabler for tunnels, such that all get the same label in case of renaming.
• Fixed bug preventing TTL 7442, 7443 and 7444...

• Fixed Preferences/Window "Reset window layout to defaults" not doing much.
• Fixed Gradle builder failing to compile LSe if sources were not checked out from Git.
• You can now swap the placement of main canvas and component tree/properties pane.
• Added Chinese translation.
• Several bug fixes.

• Logisim has now an internal font-chooser to comply to the font-values used
• Several bug fixes