riscv-boom

This marks the initial release of SonicBOOM (or BOOM v3.0.0). SonicBOOM 3.0.0 can achieve 6.2 CoreMark/MHz..

This is a concurrent release with Chipyard 1.3.

As this is a major BOOM release and update, this release note will summarize both changes since BOOMv2.2.3 (the last versioned release) and BOOMv2.0.0 (the last major release).

**Changes since B...

This marks BOOM version 2.2.3.

This is a concurrent release with Chipyard 1.1 (see github.com/ucb-bar/chipyard). Major changes include, bumping to newer Rocket Chip, improved DCache, and various bug-fixes for Linux + Fedora boot.

Changes:

• Connect clock + reset to trace port (#433 )
• Cleanup poison bit propagation (#395)
• Bump to Rocket Chip Aug. 19th version (#425 #422 #423 ) -...

This marks BOOM version 2.2.2. The significant change is deprecation of boom-template, to switch to the unified Chipyard development platform, which incorporates flows for RTL simulation, FPGA simulation through FireSim, and physical design through HAMMER. The process to design custom BOOM-based SoCs is greatly simplified.

Chipyard usage is very similar to boom-template. See the Chipyard d...

This marks BOOM version 2.2.1.

Changes:

• Deprecate unpipelined integer multiply
• Support RV32 BOOM
• Fix RVC for banked I$ configs
• Support no VM
• Clean up backend functional unit generation
• Support unified MEM and INT issue queues
• Fix FTQ clearing for flushes
• Other various RVC fixes
• Decouple load/store issue queue sizes
• Support wide floating point

This...

This marks BOOM version 2.2.0.

Changes:

• All configurations now support RISC-V compressed ("RVC") instructions
• PMP registers are enabled
• The NBDCache has been forked from rocket-chip
• Minor CSR instruction fixes
• ReadTheDocs documentation available at https://docs.boom-core.org/en/latest/
• CircleCI continuous integration
• Switch to Chisel3 syntax
• Updates for Sept...