[events] make fields public for tapping signals (https://github.com/chipsalliance/rocket-chip/pull/2464, https://github.com/chipsalliance/rocket-chip/pull/2524)
[i$] fix ccover bug to cover all beats of D channel corruption https://github.com/chipsalliance/rocket-chip/pull/2755
[d$] updates
fix elaboration with < 4 MiB of physical address space (https://github.com/chipsalliance/rocket-chip/pull/2367)
guarantee no-alloc accesses are ordered even if aliased (https://github.com/chipsalliance/rocket-chip/pull/2358)
[ecc] fixed a rare bug where under the right conditions stores to the same word resulted in one store detecting an error while the other does not (https://github.com/chipsalliance/rocket-chip/pull/2458)
[HellaCache] introduce subWordBits param to support subbanking (https://github.com/chipsalliance/rocket-chip/pull/2645)
support specifying cache index when aliasing is possible (https://github.com/chipsalliance/rocket-chip/pull/2697, https://github.com/chipsalliance/rocket-chip/pull/2730)
reduce latency on inclusion and coherence misses by allowing D$ to voluntarily release (aka "noisy drop") cache lines (https://github.com/chipsalliance/rocket-chip/pull/2696)
follow-up to fix deadlock (https://github.com/chipsalliance/rocket-chip/pull/2714)
follow-up to fix performance (https://github.com/chipsalliance/rocket-chip/pull/2739)
distinguish a supervisor mode that does not use MMU/VM (https://github.com/chipsalliance/rocket-chip/pull/2422, #2499)
[hartid]
fixed an issue where the Rocket core's placement would be impacted by non-constant hartid (https://github.com/chipsalliance/rocket-chip/pull/2432)
add a diplomatic node for assigning hartid (https://github.com/chipsalliance/rocket-chip/pull/2447)
[Replacement][PseudoLRU] fix performance issue with PseudoLRU for replacements when number of ways is not a power of 2 (https://github.com/chipsalliance/rocket-chip/pull/2493, #2498)
[Replacement][d$] configure replacement policy with parameter to indicate wheteher policy is used on a per-set basis or a global basis (https://github.com/chipsalliance/rocket-chip/pull/2656)
[PTW]
replace round robin arbitration with static arbitration (https://github.com/chipsalliance/rocket-chip/pull/2433)
fixed a bug where an L2TLB write would almost always block the next L2TLB search when MMU and clock gating were enabled (https://github.com/chipsalliance/rocket-chip/pull/2601)
wait for L2TLB to refill before searching (https://github.com/chipsalliance/rocket-chip/pull/2619)
[PTWPerfEvents] add (unused) Performance Monitor Events for L2TLB hit and PTE Cache Miss/Hit (https://github.com/chipsalliance/rocket-chip/pull/2668, https://github.com/chipsalliance/rocket-chip/pull/2688, https://github.com/chipsalliance/rocket-chip/pull/2692)
[SynchronizerPrimitiveShiftReg] correct the dedup behavior for the *ResetSynchronizerPrimitiveShiftReg so you only end up with one copy (https://github.com/chipsalliance/rocket-chip/pull/2547)
add partial multiple reset scheme support (https://github.com/chipsalliance/rocket-chip/pull/2375)
AsyncResetReg: use chisel3 async resets (#2397)
Async Reset support for Atomics, FPU, and TLBroadcast (https://github.com/chipsalliance/rocket-chip/pull/2362)
[ResetStretcher][PRCI] add reset stretcher for Async Reset systems (https://github.com/chipsalliance/rocket-chip/pull/2566)
ClockGroupDriverParameters: allow for a configurable drive function for driving asynchronous clock groups with IO other than the implicit clock (https://github.com/chipsalliance/rocket-chip/pull/2319)
[ClockDivider] fixed bug where clock divider's source and sink functions always divided by two (https://github.com/chipsalliance/rocket-chip/pull/2610)
[InterruptBusWrapper] update synchronizer API https://github.com/chipsalliance/rocket-chip/pull/2640
replaces using IntXing in a synchronize method with to and from methods
this is to ensure synchronized registers are always put in the destination clock domain
Tile
[notification] provide reset values for cease and wfi (https://github.com/chipsalliance/rocket-chip/pull/2449)
[notification][CSR] Block wfi, halt, cease, and other valid signals during asynchronous reset (https://github.com/chipsalliance/rocket-chip/pull/2611)
trace.valid of CSR changed to async-reset delay (https://github.com/chipsalliance/rocket-chip/pull/2613)
[notification][WFI] expose WFI from core (https://github.com/chipsalliance/rocket-chip/pull/2315)
[i$] fixed bug where cease signal was asserted before potential glitching in I$ clock finished. Add an assertion to cease signal. (https://github.com/chipsalliance/rocket-chip/pull/2419/, https://github.com/chipsalliance/rocket-chip/pull/2420/, https://github.com/chipsalliance/rocket-chip/pull/2456/)
[PMP][DTS] add pmp granularity to DTS (https://github.com/chipsalliance/rocket-chip/pull/2661)
Topology changed from static traits to CDE-based configurable runtime (https://github.com/chipsalliance/rocket-chip/pull/2327)
HasHierachicalBusTopology trait replaced with two config options:
WithCoherentBusTopology
WithIncoherentBusTopology
renamed attachment API to location API (https://github.com/chipsalliance/rocket-chip/pull/2330)
[BundleBridge] to propagate [TileInputConstants]. ROM attachment changes (https://github.com/chipsalliance/rocket-chip/pull/2521 merged as https://github.com/chipsalliance/rocket-chip/pull/2531)
HasPeripheryBootROM and HasPeripheryBootROMModuleImp are removed and replaced by a call to BootROM.attach
BootROMParams Field is removed and replaced with BootROMLocated Field
MaskROMLocated Field is added
SubsystemExternalResetVectorKey, SubsystemExternalHartIdWidthKey and InsertTimingClosureRegistersOnHartIds Fields are added
Unused ResetVectorBits Field is removed
HasExternallyDrivenTileConstants bundle mixin is removed
HasResetVectorWire subsystem trait is removed
HasTileInputConstants and InstantiatesTiles subsystem traits are added
BaseTile exposes val hartIdNode: BundleBridgeNode[UInt] and resetVectorNode: BundleBridgeNode[UInt] and these are automatically connected to in HasTiles.
rocket.Frontend, rocket.ICache, rocket.DCache, rocket.NDCache now have BundleBridgeSink[UInt] for their reset vector or hartid wire inputs.
If you instantiate them manually, i.e. not using the traits e.g. rocket.HasHellaCache, you will have to manually connect up those nodes to the aforementioned BaseTile nodes.
follow up PR - bug fix for HartID and ResetVector width calcluation (https://github.com/chipsalliance/rocket-chip/pull/2543/)
add HierarchicalLocation to LocationAPI (https://github.com/chipsalliance/rocket-chip/pull/2346/)
[RocketCrossingParams] relax type of master param to TilePortParamsLike (https://github.com/chipsalliance/rocket-chip/pull/2634/)
[Subsystem] Miscellaenous subsystem bus crossing changes (https://github.com/chipsalliance/rocket-chip/pull/2724)
introduce keys for bus crossings
allow for disabling of DriveClockFromMaster behavior
introduce MBus crossing to CoherentBusTopology
[Subsystem][PLIC] avoid using implicit clock (https://github.com/chipsalliance/rocket-chip/pull/2719)
Add an optional TileInputConstant as an MMIO Address Prefix used in ITIM and DTIM hit calculations (https://github.com/chipsalliance/rocket-chip/pull/2533)
[stage] Fix a bug where unserializable RocketTestSuiteAnnotations were being serialized (https://github.com/chipsalliance/rocket-chip/pull/2424)
[stage] Fix a bug where the desired output file name was being superseded by another phase (https://github.com/chipsalliance/rocket-chip/pull/2424)
[RocketChipStage] Remove emitVerilog, emitFirrtl, and emitChirrtl methods from RocketChipStage (https://github.com/chipsalliance/rocket-chip/pull/2481)
[stage] expose Stage's --target-dir to Config (https://github.com/chipsalliance/rocket-chip/pull/2725)
[Transforms][Lint] add RenameDesiredNames transform and LintConflictingModuleNames Lint rule (https://github.com/chipsalliance/rocket-chip/pull/2452)
also adds RenameModulesAspect that can be used to emit name overrides and a LintConflictingModuleNamesAspect to collect DesiredNameAnnotations to be checked by the lint pass.
[ElaborationArtefactAnnotation] add ElaborationArtefactAnnotation - an API similar to ElaborationArtefacts (#2727)
this API is for assuring metadata has correct instance paths and signal names
allow renames to multiple targets for MemoryPathToken (https://github.com/chipsalliance/rocket-chip/pull/2729)
Debug
mcontext and scontext CSRs for breakpoint qualification (https://github.com/chipsalliance/rocket-chip/pull/2588/)
allow a fast debugger reading dmstatus in a single dminner clock cycle to read the proper value (https://github.com/chipsalliance/rocket-chip/pull/2412)
fix address sent from DM to SB2TL (https://github.com/chipsalliance/rocket-chip/pull/2559)
add bus blocker to deny requests to dmInner when dmactive = 0 (https://github.com/chipsalliance/rocket-chip/pull/2205)
[TLParameters] functions to look at emits parameters (https://github.com/chipsalliance/rocket-chip/pull/2572)
[Parameters] replace cover function with mincover (https://github.com/chipsalliance/rocket-chip/pull/2571)
[APBToTL] only assert address alignment when data is ready and valid on a-channel (https://github.com/chipsalliance/rocket-chip/pull/2314)
[TLBroadcast][TLSourceShrinker][TLCacheCork][SBA][$] Drive or pass through TL user bits (#2457, #2448, #2383, #2446)
[TLBroadcast] add API to create Probe filters for Broadcast coherence manager (https://github.com/chipsalliance/rocket-chip/pull/2509)
[TLBroadcast] fixed a Generator bug when instantiated with no inner cache (https://github.com/chipsalliance/rocket-chip/pull/2516)
[TLBroadcast] Add control parameters for control interface (https://github.com/chipsalliance/rocket-chip/pull/2519)
make it possible to filter with Banked Broadcast Hub (https://github.com/chipsalliance/rocket-chip/pull/2545)
[TLSourceShrinker] preserve meta data when no shrinkage is required (#2466)
[TLFragmenter] ensure Fragmenter raises corrupt signal when raising denied (#2468)
[Tilelink][Arbiter][Xbar][ReadyValidCancel] Add new API that replaces valid with earlyValid and lateCancel to fix a timing path for A-channel requests (https://github.com/chipsalliance/rocket-chip/pull/2480, https://github.com/chipsalliance/rocket-chip/pull/2488)
[AHBToTL] retain AHB hrdata even during error response (https://github.com/chipsalliance/rocket-chip/pull/2512)
[AHBToTL] fix spurious fire of assertion on first cycle (https://github.com/chipsalliance/rocket-chip/pull/2523)
[CreditedIO] introduce new DecoupledIO interface for credit debit buffers (https://github.com/chipsalliance/rocket-chip/pull/2555)
[IdMap][IdMapEntry] standardize IdMap and IdMapEntry (https://github.com/chipsalliance/rocket-chip/pull/2483)
[AXI4IdIndexer] later fixed a bug with graphml parsing metadata bracketed in "< >" (https://github.com/chipsalliance/rocket-chip/pull/2638)
[IdMapEntry][OMIdMapEntry] add maxTransactionsInFlight field https://github.com/chipsalliance/rocket-chip/pull/2627
Diplomacy
versioning support for tilelink parameters (https://github.com/chipsalliance/rocket-chip/pull/2320)
allow users to access Lazy Module nodes (https://github.com/chipsalliance/rocket-chip/pull/2301)
JunctionNodes now support configurable up/down ratio (https://github.com/chipsalliance/rocket-chip/pull/2430)
dynamic and remote order: fix QoR in designs with large physical address maps (https://github.com/chipsalliance/rocket-chip/pull/2461)
[AddressSet] fix a bug where duplicated AddressSets would cause incorrect widening when unify is called. (#2502)
[LazyModule]
mark LazyModules for inlining such as nodes with circuit identity (inputs are outputted unchanged) (https://github.com/chipsalliance/rocket-chip/pull/2579)
make RC more tolerant to x-prop (https://github.com/chipsalliance/rocket-chip/pull/2659)
[util][rotate] fix rotate for zero-width wires (https://github.com/chipsalliance/rocket-chip/pull/2663)
[SimJTAG][SimDTM] fix a verilator bug due to delay statements (https://github.com/chipsalliance/rocket-chip/pull/2635)
register coverage now generated based on access type (https://github.com/chipsalliance/rocket-chip/pull/2384)
[BundleMap] improved API for user bits
Customizable field unification, Default for bulk assignments, Field and Key class required (https://github.com/chipsalliance/rocket-chip/pull/2318)
Use BundleMap for AMBA protocols (https://github.com/chipsalliance/rocket-chip/pull/2326)
various bug fixes to TL user fields (https://github.com/chipsalliance/rocket-chip/pull/2335)
[FixChisel3] Added some scaladoc commentary to the operators :<>, :<=, :=> to explain what they do and the rationale for their creation. (#2339)
[util] Add utilities for bitwise shifts by signed shift amounts (#2477)
[TLBusWrapper] more stability to internal wire names (https://github.com/chipsalliance/rocket-chip/pull/2515)
[LazyRoCC] convert LazyRoCC to chisel3 (https://github.com/chipsalliance/rocket-chip/pull/2553)
[OptimizationBarrier] give the module a name in generated verilog (#2507)
add test enable pin to Clock Gate (https://github.com/chipsalliance/rocket-chip/pull/2087)
[RecordMap] addd as an API for better diplomatic IO naming https://github.com/chipsalliance/rocket-chip/pull/2486
used to get easier to follow Clock Group signal names https://github.com/chipsalliance/rocket-chip/pull/2528
[IDPool] enable ResetAsynchronous Full (https://github.com/chipsalliance/rocket-chip/pull/2568)
[IDPool] add lateValid and revocableSelect to shift the deep logic cones from before the valid/selec registers to after the bitmap register (https://github.com/chipsalliance/rocket-chip/pull/2673, https://github.com/chipsalliance/rocket-chip/pull/2677)
[SCIE] fix width mismatch assignment lint warning from VCS (https://github.com/chipsalliance/rocket-chip/pull/2563)
Initial scalatest flow support and aspect generation (https://github.com/chipsalliance/rocket-chip/pull/2309/, https://github.com/chipsalliance/rocket-chip/pull/2517)