rocket-chip

Version 1.6.0

Added

• Support for Chisel 3.5.3 (https://github.com/chipsalliance/rocket-chip/pull/2931, https://github.com/chipsalliance/rocket-chip/pull/2937, https://github.com/chipsalliance/rocket-chip/pull/2947, https://github.com/chipsalliance/rocket-chip/pull/3005)
• Support for Scala 2.12.15 (https://github.com/chipsalliance/rocket-chip/pull/2947)
• Properly-sized don't cares f...

Rocket

• [CSR] add vcsr and move vxrm/vxstat from fcsr to that register set (https://github.com/chipsalliance/rocket-chip/pull/2400, #2422)
• [CSR] disallow writes to MSTATUS.XS (https://github.com/chipsalliance/rocket-chip/pull/2508)
• [CSR] expand TracedInstruction.cause to xLen (https://github.com/chipsalliance/rocket-chip/pull/2548)
• [CSR][mstatus] implement updated MPRV from priv-1....

• DCache prioritizes misaligned above guest/page fault (#2926)
• Add hypervisor extension (#2841)
• MMU: final pte.permission page fault > final pte.ppn access exception (#2916)
• PTW: Non-leaf PTEs with D/A/U==1 are reserved (#2905)
• NMI spec updates: removed UNMI, added new mnie bit to mnstatus (#2904)
• PTW: timing L2TLB valid select write way (#2868)
• PTW timing: L2TLB PLRU select writ...